1. Field of the Invention
The invention relates to a protocol processing system, particularly to an extensible protocol processing system.
2. Description of the Related Art
Conventionally, by enlarging the capacity of the buffer of the network interface controller, the transmission rate and/or the size of maximum transmission unit (MTU) or the combinations, network speed can be easily boosted. However, as the transmission rate of the Ethernet network is continuously increased and, presently, over 1 Gbps, a network interface controller with more acceleration functions of protocol processing is required. For the transmission rate over 10 Gbps, without the acceleration function of protocol processing, the bandwidth utilization rate of the network decays because the software is not capable of processing the huge amount of network packets per unit time, and the worse, the software cannot even focus on its original assigned tasks, for example, as a file server.
Among many network protocols, TCP/IP is the most popular protocol used for network applications. For example, the TCP/IP is used in Web service, audio and video service, storage service and remote service. In the present, the above-mentioned services are processed by personal computer or server, and most of executing procedures are processed by software, for example the packet encapsulating and decapsulating. In consumer electronics and digital electronic equipments, using these services is a trend. This trend results in needs for some acceleration functions which directly packaged in a single IC in the bandwidth under 1 Gbps. However, in order to get useful for more applications, such acceleration functions, which get used to be called Protocol Processing Engine and usually be implemented as intellectual properties, must be designed with extensibilities.
The applications of the above-mentioned intellectual property includes Storage Area Network (SAN), Network Attached Storage (NAS) devices, Web server, file server, remote boot, VoIP and any other applications which need to connection to moderate high speed network but, at the same time, do not want to spend too much processing time in the corresponding network protocol handling. Above all, in networks of 10 Gbps bandwidth, such an intellectual property is considered as a must despite of any assumptions. These reasons make the application range of such an intellectual property so wide.
Referring to the U.S. Pat. No. 6,434,620, it shows a structure of a protocol processing engine. The protocol processing engine is a recursive processing procedure. In the recursive processing procedure, the packet of each network layer comprises a header and a payload. Referring to the U.S. Pat. No. 2004/0243723 A1, filed by Intel Corporation, it shows a processor of high performance, the processing procedure of the protocol processing engine and the management of the socket in the operation system.
Referring to the U.S. Pat. No. 6,591,302, it shows a fast-path apparatus for receiving data corresponding to a TCP connection. The apparatus assembles a header required for each protocol processing layer from a protocol stack, combines the header and an appropriate size of data and sends the combination to the next network layer. Referring to FIG. 5A, it shows transmission process in U.S. Pat. No. 6,591,302. A session sequencer sends the data to a transport sequencer via a multiplexer. The transport sequencer adds H1 headers in a packet buffer of divided transport segments to form transport packets. The transport packets are delivered to a network sequencer via the multiplexer, and the Ethernet packets are delivered to the next network layer repetitively.
Referring to FIG. 5B, it shows the receiving process in the U.S. Pat. No. 6,591,302. The protocol processing in each layer extracts the headers from the packets received and compares them with connection data stored in the protocol stack to find a connection relation with the preceding layer, and the remaining payload data of this transmission is combined and sent to an upper layer of the protocol processing. A packet control sequencer confirms that the Ethernet packets are received from the MAC sequencer, and a multiplexer sends the packets received to a network sequencer to remove their H3 headers and combines the remainder and payload packets in a same network layer for further unpacking.
An RISC microprocessor with a protocol offload engine disclosed in U.S. Pat. No. 6,591,302 can speed up protocol offload performance but cannot easily obtain heavy complicated protocol errors and associated error recovery, which leads to a disadvantage of firmware cost increase. The errors occupy a slight part of the entire packets, but deeply affects the CPU load when certain errors not necessarily interrupting the host CPU cannot be filtered effectively.
An SRAM disclosed in U.S. Pat. No. 6,591,302 is responsible to offload operation and performance. Any packet or data not able to offload immediately is moved from the SRAM to an DRAM having greater room and lower cost in order to wait until all other packets or information is arrived. Next, all information arrived is moved from the DRAM to the SRAM for offload performance. As such, it can simplify the offload engine design and the complexity of internal data path. However, data moved between the SRAM and the DRAM can relatively consume the bandwidth of internal circuits. In addition, the SRAM may lead to a bandwidth bottleneck. For a network bandwidth of 1 Gbps, a full duplex protocol offload engine needs a bandwidth of 2 Gbps, but a high-speed dual-port SRAM is expensive.
Consequently, there is an existing need for a protocol processing system to solve the above-mentioned problem.